1. Field of the Invention
The present invention relates to electrically erasable and programmable memories.
The present invention more particularly relates to an erasable and programmable memory, comprising memory cells, each incorporating a floating gate transistor connected in series with MOS access transistor.
2. Description of the Related Art
FIG. 1 represents an example of EEPROM memory cell of the type mentioned hereinbefore, comprising a floating gate transistor FGT which drain terminal is connected to the source terminal of an access transistor AT. The gate terminal of the AT transistor is connected to a word line R and the drain terminal of the AT transistor is connected to a bit line BL.
FIGS. 2A and 2B show the cell represented in FIG. 1 in top view and cross-sectional view, respectively. The cell is embedded in a substrate type p in which three regions 1, 2, 3 doped n+ are formed, respectively constituting the region of the drain of the FGT transistor, the region of the source of the AT transistor, and eventually the region of the drain of the AT transistor. The memory cell comprises:
a source terminal SC of the transistor FGT, embedded on the source region 1 of the FGT transistor,
a floating gate FG and a control gate CG of the transistor FGT, superimposed, which are formed above an intermediate region between regions 1 and 2, and above a portion of region 2,
a gate terminal R of the AT transistor formed above an intermediate region between regions 2 and 3, and
a drain terminal BLC of the AT transistor, formed on the drain region 3 of the AT transistor.
The operation of such a memory cell is based upon the tunneling effect (or Fowler-Nordheim effect) and consists in causing moves of the threshold voltage of the FGT transistor by transferring or removing charges into/from the floating gate FG through a thin oxide layer located between the doped region 2 and the floating gate. An erasing or programming operation of the memory cell consists of injecting or extracting electrical charges into/from the floating gate of the FGT transistor by Fowler-Nordheim effect. The FGT transistor has a threshold voltage VT1 (equal to approximately −2 V) in programming state, and a threshold voltage VT2 superior to the voltage VT1 (equal to approximately 4 V) in erasing state. When a read voltage Vread comprised between VT1 and VT2 is applied to its control gate CG, the transistor FGT remains in blocking state if it is erased, which conventionally corresponds to a logic “0”, and it is in conducting state if it is programmed, which corresponds to a logic “1”. It will be understood that an inverse convention can be retained.
FIG. 3 represents an example of EEPROM memory of the type mentioned hereinbefore. The memory comprises groups of M memory cells, each group being able to memorize a word of M bits (8 in the example of the figure, that is, a byte). For simplicity reasons, this figure only represents one group of memory cells, belonging to a column of rank k and to a word line R(i) of rank i. This group of memory cells arranged in line comprises a control gate transistor CGT which source terminal is connected to all the gates terminals of the transistors FGT of the group, and which gate terminal is connected to all the gates terminals of the access transistors AT of the group and to a selection line SEL(i). The sources terminals of the FGT transistors of the memory cells are connected to a global source line SL, usually controlled by a simple transistor which switches it to ground or to high impedance. Each of the drains terminals of the AT transistors of the group is connected to a bit line BL(j,k) (j being an integer between 0 and M-1). The CGT transistor provides the connection of the gates terminals of the FGT transistors of the group of memory cells with a control gate line CG(k) of the group. That way, the cells can be erased in parallel by putting them in a state conventionally associated to the value 0, the state in which they have a threshold voltage of high value.
The operations of erasing and programming memory cells are carried out thanks to latches of bit line BL(j,k) gathered into sets of latches of bit line BLL, latches of control gates lines CGL, one word lines decoder RDEC having one output per word line R(i), and one column control unit SD.
FIG. 4 represents a set of 8 groups of memory cells, as represented in FIG. 3, each group being able to memorize a word. On that figure, the groups are gathered into columns of ranks k, k+1 and into word lines of ranks i−1, i, i+1, i+2. Thus, each selection line SEL(i) is connected to the gates terminals of the AT transistors of the groups located on the same line. The source lines of the groups of each column are connected to a global source line SL.
Collective erasing of the FGT transistors of a group of memory cells belonging to a word line of rank i and a column of rank k, is carried out by applying a voltage Vpp1, of 12 V for example, on the control gate CG of the FGT transistors, via the control gate transistor CGT of the group, while the source line SL is applied 0 volt and the drain terminal of the FGT transistors via the access transistors AT is at a floating potential or high impedance. Individual programming of FGT transistors is carried out by applying the Vpp1 voltage to the drain terminals of the FGT transistors via the access transistors, while the control gate of the FGT transistors is at 0 volt, and the source line SL is applied a floating potential.
The table 1 below sums up the values of the control signals applied during the operations of erasing, programming and reading of memory cells.
TABLE 1OperationControl signalERASINGPROGRAMMINGREADINGSEL(i)Vpp2Vpp2VDCSEL(l) (l ≠ i)VrefVrefVrefCG(k)Vpp1VrefVreadCG(n) (n ≠ k)FloatingFloatingFloatingBL(j, k)FloatingVpp1VsenseBL(m, n) (m ≠ j, n ≠ k)FloatingFloatingFloatingSLVrefFloatingVref
In that table, the voltage Vref is equal to 0 V (ground), the voltage Vpp2 is equal to 15 V, the voltage VDC is comprised between 3 and 5 V, the voltage Vread is comprised between the threshold voltages VT1 and VT2 and the voltage Vsense is of approximately 1 V.
The currents resulting from the Fowler-Nordheim tunneling effect in the FGT transistors mainly depend on the thickness of the tunnel oxide layer between the doped region 2 and the floating gate FG, and on the electrical field which is proportional to the voltage applied to the floating gate transistor FGT and to the capacitive coupling factor between its floating gate FG and its control gate CG, compared to the coupling of the latter with the drain terminal and the source terminal of the transistor, as well as with the rest of the cell.
It is known that the threshold voltage VT of a floating gate transistor increases if the applied voltage and the coupling factor are increased, and if the thickness of the oxide layer is decreased. However, reducing the thickness leads to reducing the period during which the floating gate can keep its charge, that is, the time for the memory cell to memorize data, which should be of several years. Consequently, so as to increase the speed of the memory, or to reduce the length of programming and erasing operations, the applied voltages should be increased and the coupling factor should be reduced. The coupling factor is hard to reduce and especially if there is an attempt to reduce the size of the memory cells at the same time. The increase of the voltages applied to the memory cells is also limited by the breakdown voltage of the drain or source junctions between the regions doped n+ and the substrate p. The breakdown voltage depends on the technology used. In the example described hereinbefore, the breakdown voltage is slightly superior to 12 V. Therefore it is not possible to submit the junctions (drain-gate) of the transistors to voltages deviations superior to 12 V.